The Execution Cycle Simulation - part III


When you start the simulation you will see the CPU with the program counter, instruction register, memory address register and the Accumulator on the left of the screen, ROM on the right and the address bus (blue), data bus (green) and the control bus (red) in between.

Refreshing the page, which simulates power-down followed by power-up, does not change the contents of ROM because ROM is nonvolatile.

However, the data on the busses at this point is random.

This simulation is for a fictitious microcontroller with a very limited instruction set which is given in the table below.

Assembly HEX Equivalent Operation Size of Instruction
INC A E4 A <- A + 1 1 byte
DEC A E5 A <- A - 1 1 byte
LD A, data 3E data A <- data 2 bytes
JP address D6 address PC <- address 3 bytes
JP Z, address D7 address

if A = 0 PC <- address
if A != 0 PC <- PC + 3

3 bytes

Note: the difference between part 2 and part 3 of the Execution Cycle Simulations is the inclusion of a conditional jump in part 3, as can be seen is the last entry in the above instruction set.

The following short program is assembled into machine code and placed in ROM.

ORG 0130H
LD A, 03H
JP Z, 0130H
JP 0132H

As can be seen in the simulation, ROM contains:

  0 1 2 3 4 5 6 7 8
0130 3E 03 E5 D7 30 01 D6 32 01

Step through the simulation by clicking on Next -> and watch as each instruction is decoded and executed.


Copyright (c) 2005-2013 James Rogers