The Read and Write Cycle Simulations

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The following simulation helps students understand the concepts of random access memory and the read and write cycles.

When you start the simulation you will be presented with the CPU on the left of the screen and the memory matrix on the right, with the address bus (blue), data bus (green) and the control bus (red) in between.

Initially, memory is filled with random data, as are the address and data busses.

If you refresh the page you will notice the data changes - this simulates powering down and then powering up the system.

When the student starts the read cycle by clicking on Read he/she must first choose an address to read from and then click on CPU requests data.

Notice the data begins to settle on the address bus. This is done in a very orderly fashion (one hex digit after another), which of course is not realistic. However, it is hoped that this will demonstrate to the student that it takes a finite amount of time for the address to settle on the address bus.

The student now plays the part of the control bus by clicking on:
control signals memory: address on bus is valid ->
However, if he/she signals memory too early (before the address has settled) then the wrong location is accessed.

Once the location has been selected by RAM the student plays the part of the control bus by clicking on:
<- control signals CPU: data on bus is valid
Again, if he/she doesn't wait for the data in memory to appear on the data bus, random data is read by the CPU.

The student may then repeat the exercise for the write cycle.

Start Simulation


Copyright (c) 2005-2013 James Rogers